Field of the Invention
Embodiments of the present invention relate generally to graphics processing and, more specifically, to an approach to reducing voltage noise in a stalled data pipeline.
Description of the Related Art
In computer systems, in general, and in graphics processing units (GPUs), in particular, a pipeline consists of data processing elements performing different tasks connected in series. There is often local memory storage within the pipeline as well as access to cache elements in external memory. The normal flow of data can temporarily stop due to a number of possible causes, such as, but not limited to, availability of data, the need to perform more extensive local processing before proceeding, the need to access data from external memory, or momentary limitations in the ability to process incoming or outgoing data. When such a stall occurs, data processing circuits become idle, and the power usage consequently decreases significantly. Conversely, when the stall condition clears and traffic resumes, the backlog of data causes a transient surge in power consumption as all, or many, circuits become active simultaneously to process the resultant rush of data.
This surge in power consumption causes a transient increase in current, referred to as di/dt, or change in current with respect to time. Due to the di/dt event, excessive current is drawn from the power supply, which causes a local droop or sag in the voltage level at the circuit elements involved. After the initial rush has been processed, the rate of data traffic returns to typical levels, di/dt subsides, and voltage supply level returns to an average or typical value. A worst case analysis for a unit or microcircuit must include margin for the transient dip in voltage at all the cells potentially involved in, or nearby, a stall event.
One drawback to the above approach is that the worst case analysis results in a minimum voltage seen by the circuit elements over time and temperature variations, and this minimum supply voltage is a driving parameter in determining the maximum frequency of operation of the pipeline. As a lesser supply voltage level results in a reduced maximum clock frequency, di/dt events reduce the maximum operating frequency which, in turn, reduces processing speed, a critical performance specification of computer systems and GPUs. In addition, the reduced clock frequency due to di/dt events in one pipeline propagates across the entire system, in that the reduced clock frequency applies globally.
Accordingly, what is needed in the art is an approach or technique for reducing the occurrence, or limiting the severity, of di/dt events within a processing pipeline.